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Speed-up your FPGA Verification.


TIGER has been developed by Intelligent Systems / Altran as a tool to manage verification and validation of safety-critical FPGA. TIGER increases quality and efficiency of this important phase.

Verification and validation processes are mandatory in standards such as ECSS-Q60 and DO-254 to turn an FPGA design into a safety critical design, when complex logic has to be implemented in hardware.

TIGER includes:

  • Test-benches: a VHDL framework to quickly setup an engine that parses input files (written in low level language). These files describe stimulus and expected behaviors. Results are printed in an output file
  • Integration: a compiler that integrates high level meta-language in the lower levels to facilitate development
  • Graphical User Interface: to quickly compose the test plan, choose the subset of tests to be executed and launch the VHDL simulator (generally ModelSIM)
  • Enhanced Reports: Tags inserted in the test descriptions, and referencing the requirements, are automatically parsed by the VHDL engine and added to the test reports. This feature allows automatic build of the traceability matrix with tool like ReqTracer or Reqtify


Costs-efficient support for V&V of FPGA is a known issue to FPGA and ASIC designers.

Intelligent Systems / Altran created TIGER to answer the needs of clients involved in design of Safety Critical FPGA (e.g. ECSS-Q60, DO-254).

TIGER enables faster writing of VHDL test-benches as a result of the following features:

  • There are many standards such as SystemC or System Verilog but there is no standard widely accepted, especially for safety critical design.
  • TIGER is not a new standard to be qualified but a set of applications to develop test-benches based on traditional methodology (VHDL as code language and ModelSim as simulator)
  • The engine framework written with a modular architecture can support as is different type of FPGA implementations but it can be easily adapted to new needs such as integration of a new type of bus or use of new Validation IP
  • The structure made by a static VHDL engine, and text input files describing test sequences, allows freeze of VHDL in the early phases of the project, hence reducing the impact of multiple versioning.

Case Reference

TIGER used in several projects such as:

  • on-board-computer for a space mission (ECSS-Q60) 
  • actuator system for a military helicopter (DO-254 DAL A) 


Deliver Safety Critical FPGAs according to regulations performing requirement traceability (including test plan and test report) and code coverage.


The use of TIGER reduced by 15% the time of test-benches development, and helped to automatically generate the cross matrixes for traceability between requirement, test plan and test reports.